To solve this problem Inmos also provided a zero-delay switch that connected up to 32 transputers (or switches) into even larger networks.
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The basic design of the transputer included serial links that allowed it to communicate with up to four other transputers, each at 5, 10, or 20 Mbit/s - which was very fast for the 1980s. Any number of transputers could be connected together over links (which could run tens of metres) to form one computing farm. A hypothetical desktop machine might have two of the "low end" transputers handling input/output (I/O) tasks on some of their serial lines (hooked up to appropriate hardware) while they talked to one of their larger cousins acting as a CPU on another. This serial link is called an os-link.
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The first transputers were announced in 1983 and released in 1984. In keeping with their role as microcontroller-like devices, they included on-board RAM and a built-in RAM controller which enabled more memory to be added with no added hardware. Unlike other designs, transputers did not include I/O lines: these were to be added with hardware attached to the existing serial links. There was one 'Event' line, similar to a conventional processor's interrupt line.
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Atari Transputer Workstation is a standalone machine developed in conjunction with Perihelion Hardware, containing modified ST hardware and up to 17 transputers capable of massively parallel operations for tasks such as ray tracing.
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The multiuser envirorunent could support up to eight users by using Parsytec's multiple virtual architecture software. The NCU design was based on the Inmos crossbar switch, the C004, which gives full crossbar connectivity for up to 16 transputers. Each NCU, made of C004s, connected up to 96 UniLinks that link internal as weil as external transputers and other I/0 subsystems. MultiCluster-2 provided the ability to configure a variety of fixed interconnection topologies such as tree or mesh structures.
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The Sun acted as "front-end" host system for managing the transputers, running development tools and providing mass storage. A version of M²VCS running as a SunOS daemon called SVCS (Sun Virtual Computing Surfaces) provided access between the transputer network and the Sun host. As the performance of the transputer became less competitive towards the end of the 1980s (the follow-on T9000 transputer being beset with delays) Meiko added the ability to supplement the transputers with Intel i860 processors.
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Inmos saw them being used for practically everything, from operating as the main CPU for a computer to acting as a channel controller for disk drives in the same machine. Spare cycles on any of these transputers could be used for other tasks, greatly increasing the overall performance of the machines. Even one transputer would have all the circuitry needed to work by itself, a feature more commonly associated with microcontrollers. The intent was to allow transputers to be connected together as easily as possible, with no need for a complex bus, or motherboard.
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In 1985, when INMOS management suggested the release of the transputer be delayed, Miles Chesney, David Alden, Eric Barton, Roy Bottomley, James Cownie and Gerry Talbot resigned and formed Meiko (Japanese for "well-engineered") to start work on massively parallel machines based on the processor. Nine weeks later they demonstrated a transputer system based on experimental 16 bit transputers at the SIGGRAPH in San Francisco in July 1985. In 1986 a system based on 32 bit T414 transputers was launched as the Meiko Computing Surface. By 1990, Meiko had sold more than 300 systems and grown to 125 employees.
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The German company Jäger Messtechnik used transputers for their early ADwin real-time data acquisition and control products. Transputers also found use in protocol analysers such as the Siemens/Tektronix K1103 and in military applications where the array architecture suited applications such as radar and the serial links (that were high speed in the 1980s) served well to save cost and weight in sub-system communications. The transputer also appeared in products related to virtual reality such as the ProVision 100 system made by Division Limited of Bristol, featuring a combination of Intel i860, 80486/33 and Toshiba HSP processors, together with T805 or T425 transputers, implementing a rendering engine that could then be accessed as a server by PC, Sun SPARCstation or VAX systems. Myriade, a European miniaturized satellite platform developed by Astrium Satellites and CNES and used by satellites such as the Picard, is based on the T805 yielding around 4 MIPS and is scheduled to stay in production until about 2015.
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The Atari Transputer Workstation system consists of three main parts: # the main motherboard containing a T800-20 transputer and 4MB of RAM (expandable to 16MB) # a complete miniaturized Mega ST acting as an I/O processor with 512kB of RAM # the Blossom video system with 1MB of dual-ported RAM All of these are connected using the Transputer's 20 Mbit/s processor links. The motherboard contains three slots for additional "farm cards" containing four transputers each, meaning that a fully expanded ATW contains 13 transputers. Each runs at 20 MHz (the -20 in the name) which supplied about 10 MIPS each. The bus is available externally, allowing several ATWs to be connected into one large farm.
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PARAM 8600 was an improvement over PARAM 8000. In 1992 C-DAC realised its machines were underpowered and wished to integrate the newly released Intel i860 processor. Each node was created with one i860 and four Inmos T800 transputers. The same PARAS programming environment was used for both the PARAM 8000 and 8600; this meant that programs were portable.
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The PARAM 8000 was the first machine in the series and was built from scratch. A prototype was benchmarked at the 1990 Zurich Super- computing Show: it demonstrated that India had the second most powerful, publicly-demonstrated , supercomputer in the world after the United States. A 64-node machine was delivered in August 1991. Each node used Inmos T800/T805 transputers.
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New York: Springer-Verlag. The Computing Surface architecture comprised multiple boards containing transputers connected together by their communications links via Meiko- designed link switch chips. A variety of different boards were produced with different transputer variants, RAM capacities and peripherals. The initial software environments provided for the Computing Surface was OPS (Occam Programming System), Meiko's version of INMOS's D700 Transputer Development System.
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In 1986, the T-Series hypercube computers using INMOS transputers and Weitek floating-point processors was introduced. The T stood for "Tesseract". Unfortunately, parallel processing was still in its infancy and the software tools and libraries for the T-Series didn't facilitate customers' parallel programming. I/O was also difficult, so the T-Series was discontinued, a mistake costing tens of millions of dollars that was nearly fatal to FPS.
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Although not strictly a transputer, the ST20 was heavily influenced by the T4 and T9 and formed the basis of the T450, which was arguably the last of the transputers. The mission of the ST20 was to be a reusable core in the then emerging SoC market. The original name of the ST20 was the Reusable Micro Core (RMC). The architecture was loosely based on the original T4 architecture with a microcode-controlled data path.
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Yuval Elovici was born in Beer-Sheva, Israel in 1966. He received his B.Sc. and M.Sc. degrees in computer and electrical engineering from Ben-Gurion University of the Negev in 1989 and 1991, respectively (thesis title: Multi-Target Tracking Implementation onto a Parallel Multiprocessor System based on Transputers). He received his Ph.D. from Tel Aviv University’s Faculty of Management's information systems program (dissertation title: Information Technology Evaluation, Investment Decisions and Benefits to the Organization over Time).
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Helios was predominantly intended to be used with Transputer systems. It is compatible with products from various manufacturers including INMOS' TRAM systems, the Meiko CS, Parsytec MultiCluster and SuperCluster, and the Telmat T.Node. The Atari Transputer Workstation was perhaps the highest profile Helios hardware, at least outside academia. Helios can run on T4xx and T8xx, 32-bit Transputers (but not the T2xx 16-bit models) and includes device drivers for various SCSI, Ethernet and graphics hardware from Inmos, Transtech, and others.
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Since 1992, driving in public traffic was standard as final step in real-world testing. Several dozen Transputers, a special breed of parallel computers, were used to deal with the (by 1990s standards) enormous computational demands. Two culmination points were achieved in 1994/95, when Dickmanns´ re-engineered autonomous S-Class Mercedes-Benz performed international demonstrations. The first was the final presentation of the PROMETHEUS project in October 1994 on Autoroute 1 near the airport Charles-de-Gaulle in Paris.
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ParaCom thence took care of the sales and marketing side of the business. Parsytec/ParaCom's headquarters were maintained in Aachen (Germany), however they had subsidiary sales offices in Chemnitz (Germany), Southampton (United Kingdom), Chicago (USA), St Petersburg (Russia) and Moscow (Russia).Parsytec GmbH at new-npac.org In Japan, the machines were sold by Matsushita. Between 1988 and 1994, Parsytec built quite an impressive range of transputer based computers having its peak in the "Parsytec GC" (GigaCluster) which was available in versions using 64 up to 16384 transputers.
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The transputer (the name deriving from "transistor" and "computer") was the first general purpose microprocessor designed specifically to be used in parallel computing systems. The goal was to produce a family of chips ranging in power and cost that could be wired together to form a complete parallel computer. The name was selected to indicate the role the individual transputers would play: numbers of them would be used as basic building blocks, just as transistors had earlier. Originally the plan was to make the transputer cost only a few dollars per unit.
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Treated as a channel, a program could 'input' from the event channel, and proceed only after the event line was asserted. All transputers ran from an external 5 MHz clock input; this was multiplied to provide the processor clock. The transputer did not include a memory management unit (MMU) or a virtual memory system. Transputer variants (except the cancelled T9000) can be categorised into three groups: the 16-bit T2 series, the 32-bit T4 series, and the 32-bit T8 series with 64-bit IEEE 754 floating-point support.
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TV-toy was to be the basis for a video game console and was joint project between Inmos and Sinclair Research. The links in the T212 and T414/T424 transputers had hardware DMA engines so that transfers could happen in parallel with execution of other processes. A variant of the design, termed the T400, not to be confused with a later transputer of the same name, was designed where the CPU handled these transfers. This reduced the size of the device considerably since 4 link engines were approximately the same size as the whole CPU.
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Four cameras with two different focal lengths for each hemisphere were used in parallel for this purpose. Kalman filters were extended to handle perspective imaging and to achieve robust autonomous driving even in the presence of noise and uncertainty. Sixty transputers, a type of parallel computers, were used to deal with the enormous (by 1990s standards) computational demands. In 1994, the VaMP and its twin VITA-2 were stars of the final international presentation of the PROMETHEUS project in October 1994 on Autoroute 1 near the Charles-de-Gaulle airport in Paris.
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Schulten recognized that a successful attack on modeling the photosynthetic reaction center would require parallel computing power. He used his research grants to support Munich students Helmut Grubmüller and Helmut Heller in building a custom parallel computer optimized for molecular dynamics simulations. They developed a parallel computer, the T60, containing ten circuit boards with six Transputers each, for a total of 60 nodes. The T60 was small enough that Schulten was able to carry it through customs in a backpack, when he moved to the United States to join the University of Illinois at Urbana-Champaign.
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Sun Sparcstation as front end The x'plorer model came in two versions: The initial version was featuring 16 transputers, each having access to 4MB RAM and called just x'plorer. Later when Parsytec generally switched to the PPC architecture, it was called POWERx'plorer and featured 8 MPC 601 CPUs. Both models came in the same gorgeous desktop case (designed by Via 4 DesigniF Online Exhibition - Via 4 Design at ifdesign.de). In any model, the x'plorer was more or less a single "slice" — Parsytec called them cluster (picture) — of a GigaCube (PPC or Transputer), which used 4 of those clusters in its smallest version (GC-1).
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Transputers could boot from memory as do most computers, or over network links, so one transputer could start up a whole network. There was a pin called BootFromROM that, when asserted, caused the transputer to start two bytes from the top of memory (sufficient for up to a 256 byte backward jump, usually out of ROM). When this pin was not asserted, the first byte that arrived down any link was the length of a bootstrap to be downloaded, which was placed in low memory and run. The 'special' lengths of 0 and 1 were reserved for PEEK and POKE – allowing inspection and changing of RAM in an unbooted transputer.
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The first production transputers, the T212 and T414, followed in 1985; the T800 floating point transputer in 1987. May initiated the design of one of the first VLSI packet switches, the C104, together with the communications system of the T9000 transputer. Working closely with Tony Hoare and the Programming Research Group at Oxford University, May introduced formal verification techniques into the design of the T800 floating point unit and the T9000 transputer. These were some of the earliest uses of formal verification in microprocessor design, involving specifications, correctness preserving transformations and model checking, giving rise to the initial version of the FDR checker developed at Oxford.
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Inmos improved on the performance of the T8 series transputers with the introduction of the T9000 (code-named H1 during development). The T9000 shared most features with the T800, but moved several pieces of the design into hardware and added several features for superscalar support. Unlike the earlier models, the T9000 had a true 16 KB high-speed cache (using random replacement) instead of RAM, but also allowed it to be used as memory and included MMU-like functionality to handle all of this (termed the PMI). For more speed the T9000 cached the top 32 locations of the stack, instead of three as in earlier versions. The T9000 used a five-stage pipeline for even more speed.
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Transputers were intended to be programmed using the programming language occam, based on the communicating sequential processes (CSP) process calculus. The transputer was built to run Occam specifically, more than contemporary CISC designs were built to run languages like Pascal or C. Occam supported concurrency and channel-based inter-process or inter-processor communication as a fundamental part of the language. With the parallelism and communications built into the chip and the language interacting with it directly, writing code for things like device controllers became a triviality; even the most basic code could watch the serial ports for I/O, and would automatically sleep when there was no data. The initial occam development environment for the transputer was the Inmos D700 Transputer Development System (TDS).
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These included Meiko Scientific (founded by ex- Inmos employees), Floating Point Systems, Parsytec, and Parsys. Several British academic institutions founded research activities in the application of transputer-based parallel systems, including Bristol Polytechnic's Bristol Transputer Centre and the University of Edinburgh's Edinburgh Concurrent Supercomputer Project. Also, the Data Acquisition and Second Level Trigger systems of the High Energy Physics ZEUS Experiment for the Hadron Elektron Ring Anlage (HERA) collider at DESY was based on a network of over 300 synchronously clocked transputers divided into several subsystems. These controlled both the readout of the custom detector electronics and ran reconstruction algorithms for physics event selection. The parallel processing abilities of the transputer were put to use commercially for image processing by the world's largest printing company, RR Donnelley & Sons, in the early 1990s.
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Meanwhile, HeliOS is Unix-like enough that it ran standard Unix utilities, including the X Window System as the machine's graphical user interface (GUI). In addition HeliOS runs on all of the transputers in a farm concurrently, which allows all computing tasks to be fully distributed. Powering off an ATW does not affect the overall farm, and the tasks simply move to other processors on other systems. Blossom supports several video modes: :mode 0: 1280 by 960 pixels, 16 colors out of a palette of 4096 (including 16 true grayscales, on a monochrome monitor) :mode 1: 1024 by 768 pixels, 256 colors out of a palette of 16.7 million :mode 2: 640 by 480 pixels (2 virtual screens), 256 colors out of a palette of 16.7 million :mode 3: 512 by 480 pixels, 16.7 million colors While not much by today's standards, in the 1980s this was largely unheard of.
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While the transputer was simple but powerful compared to many contemporary designs, it never came close to meeting its goal of being used universally in both CPU and microcontroller roles. In the microcontroller market, the market was dominated by 8-bit machines where cost was the most serious consideration. Here, even the T2s were too powerful and costly for most users. In the computer desktop and workstation field, the transputer was fairly fast (operating at about 10 million instructions per second (MIPS) at 20 MHz). This was excellent performance for the early 1980s, but by the time the floating- point unit (FPU) equipped T800 was shipping, other RISC designs had surpassed it. This could have been mitigated to a large extent if machines had used multiple transputers as planned, but T800s cost about $400 each when introduced, which meant a poor price/performance ratio.
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