So when Windows 3.0 broke the 640K memory barrier, and the Intel 5 processor upped the speed limit, the game was finally on.
|
|
Factors like familiarity, repetition, and emotional arousal (a state of heightened physiological activity) all help determine which experiences cross the short-term to long-term memory barrier.
|
|
These three commercial architectures exhibit explicit fence instructions as their safety nets. The Alpha model provides two types of fence instructions, memory barrier (MB) and write memory barrier (WMB). The MB operation can be used to maintain program order of any memory operation before the MB with a memory operation after the barrier. Similarly, the WMB maintains program order only among writes.
|
|
Dansdata: What's with the 3Gb memory barrier? Many versions of MS Windows can activate what is still called PAE for the purpose of using the NX bit, but this no longer extends the address space.
|
|
Since the caches mediate accesses to memory addresses, data written to different addresses may reach the peripherals' memory or registers out of the program order, i.e. if software writes data to an address and then writes data to another address, the cache write buffer does not guarantee that the data will reach the peripherals in that order. It is the responsibility of the software to include memory barrier instructions after the first write, to ensure that the cache buffer is drained before the second write is executed. Memory-mapped I/O is the cause of memory barriers in older generations of computers, which are unrelated to memory barrier instructions.
|
|
Intel has published a guide to mitigating the vulnerability by using compiler technology, requiring existing software to be recompiled to add `LFENCE` memory barrier instructions at every potentially vulnerable point in the code. However, this mitigation appears likely to result in substantial performance reductions in the recompiled code.
|
|
A write barrier in a garbage collector is a fragment of code emitted by the compiler immediately before every store operation to ensure that (e.g.) generational invariants are maintained. A write barrier in a memory system, also known as a memory barrier, is a hardware-specific compiler intrinsic that ensures that all preceding memory operations "happen before" all subsequent ones.
|
|
In many programming languages different types of barriers can be combined with other operations (like load, store, atomic increment, atomic compare and swap), so no extra memory barrier is needed before or after it (or both). Depending on a CPU architecture being targeted these language constructs will translate to either special instructions, to multiple instructions (i.e. barrier and load), or to normal instruction, depending on hardware memory ordering guarantees.
|
|
A kind of memory barrier that separates one buffer from the rest of the memory is called a fence. Fences are there to ensure that a buffer is not being overwritten before rendering and display operations have completed on it. Implicit fencing is used for synchronization between graphics drivers and the GPU hardware. The fence signals when a buffer is no longer being used by one component so it can be operated on or reused by another.
|
|
The 2 GB limit refers to a physical memory barrier for a process running on a 32-bit operating system, which can only use a maximum of 2 GB of memory. The problem mainly affects 32-bit versions of operating systems like Microsoft Windows and Linux, although some variants of the latter can overcome this barrier. It is also found in servers like FTP servers or embedded systems like Xbox. The use of Physical Address Extension (PAE) can help overcome this barrier.
|
|
When working at the hardware level, Peterson's algorithm is typically not needed to achieve atomic access. Some processors have special instructions, like test-and-set or compare-and-swap, that, by locking the memory bus, can be used to provide mutual exclusion in SMP systems. Most modern CPU s reorder memory accesses to improve execution efficiency (see memory ordering for types of reordering allowed). Such processors invariably give some way to force ordering in a stream of memory accesses, typically through a memory barrier instruction.
|
|
On most non-x86 architectures, explicit memory barrier or atomic instructions (as in the example) must be used. On some systems, such as IA-64, there are special "unlock" instructions which provide the needed memory ordering. To reduce inter-CPU bus traffic, code trying to acquire a lock should loop reading without trying to write anything until it reads a changed value. Because of MESI caching protocols, this causes the cache line for the lock to become "Shared"; then there is remarkably no bus traffic while a CPU waits for the lock.
|
|
The simple implementation above works on all CPUs using the x86 architecture. However, a number of performance optimizations are possible: On later implementations of the x86 architecture, spin_unlock can safely use an unlocked MOV instead of the slower locked XCHG. This is due to subtle memory ordering rules which support this, even though MOV is not a full memory barrier. However, some processors (some Cyrix processors, some revisions of the Intel Pentium Pro (due to bugs), and earlier Pentium and i486 SMP systems) will do the wrong thing and data protected by the lock could be corrupted.
|
|
A memory barrier, also known as a membar, memory fence or fence instruction, is a type of barrier instruction that causes a central processing unit (CPU) or compiler to enforce an ordering constraint on memory operations issued before and after the barrier instruction. This typically means that operations issued prior to the barrier are guaranteed to be performed before operations issued after the barrier. Memory barriers are necessary because most modern CPUs employ performance optimizations that can result in out-of-order execution. This reordering of memory operations (loads and stores) normally goes unnoticed within a single thread of execution, but can cause unpredictable behaviour in concurrent programs and device drivers unless carefully controlled.
|
|
In addition to setting up the environment and loading the actual program to be executed, the DOS extender also provides (amongst other things) a translation layer that maintains buffers allocated below the 1 MB real mode memory barrier. These buffers are used to transfer data between the underlying real mode operating system and the protected mode program. Since switching between real/V86 mode and protected mode is a relatively time consuming operation, the extender attempts to minimize the number of switches by duplicating the functionality of many real mode operations within its own protected mode environment. As DOS uses interrupts extensively for communication between the operating system and user level software, DOS extenders intercept many of the common hardware (e.g.
|
|
The above code would never detect such a change; without the `volatile` keyword, the compiler assumes that the current program is the only part of the system that could change the value (which is by far the most common situation). To prevent the compiler from optimizing code as above, the `volatile` keyword is used: static volatile int foo; void bar (void) { foo = 0; while (foo != 255) ; } With this modification the loop condition will not be optimized away, and the system will detect the change when it occurs. Generally, there are memory barrier operations available on platforms (which are exposed in C++11) that should be preferred instead of volatile as they allow the compiler to perform better optimization and more importantly they guarantee correct behaviour in multi-threaded scenarios; neither the C specification (before C11) nor the C++ specification (before C++11) specifies a multi-threaded memory model, so volatile may not behave deterministically across OSes/compilers/CPUs).
|
|